Difference between revisions of "CPCAP"

From MILEDROPEDIA
Jump to: navigation, search
m (→‎Code Samples)
m (→‎Code Samples)
Line 106: Line 106:
 
   cpcap_check_ULPI_and_VBUS();
 
   cpcap_check_ULPI_and_VBUS();
 
   cpcap_init_chain();
 
   cpcap_init_chain();
 +
  memclr(*(0x8FB52188), 0x80);
 
}
 
}
−
</syntaxhighlight>
 
−
 
−
<syntaxhighlight lang="ida" line>
 
−
ROM:8F31C666                ; =============== S U B R O U T I N E =======================================
 
−
ROM:8F31C666
 
−
ROM:8F31C666                ; Attributes: noreturn
 
−
ROM:8F31C666
 
−
ROM:8F31C666                ; int __fastcall pcap_init()
 
−
ROM:8F31C666                pcap_init                                                  ; CODE XREF: hardware_init+1E�p
 
−
ROM:8F31C666 000 10 B5                      PUSH    {R4,LR}                            ; Push registers
 
−
ROM:8F31C668 008 59 A0                      ADR    R0, comments_0_msg                  ; "\r\n************* \r\n"
 
−
ROM:8F31C66A 008 01 F0 F6 F9                BL      log_write                          ; Branch with Link
 
−
ROM:8F31C66E 008 5D A0                      ADR    R0, CPCAP_INIT_MSG                  ; "CPCAP_init( ) \r\n"
 
−
ROM:8F31C670 008 01 F0 F3 F9                BL      log_write                          ; Branch with Link
 
−
ROM:8F31C674 008 60 A0                      ADR    R0, comments_1_msg                  ; "************* \r\n"
 
−
ROM:8F31C676 008 01 F0 F0 F9                BL      log_write                          ; Branch with Link
 
−
ROM:8F31C67A 008 05 F0 2F FE                BL      spi_read_write_3                    ; Branch with Link
 
−
ROM:8F31C67E 008 FF F7 EA FE                BL      check_ULPI_and_VBUS                ; Branch with Link
 
−
ROM:8F31C682 008 FF F7 53 FF                BL      pcap_init_key                      ; Branch with Link
 
−
ROM:8F31C686                ; ---------------------------------------------------------------------------
 
−
ROM:8F31C686 008 80 21                      MOVS    R1, #0x80                          ; Rd = Op2
 
−
ROM:8F31C688 008 60 48                      LDR    R0, =0x8FB52188                    ; Load from Memory
 
−
ROM:8F31C68A 008 0D F0 56 EA                BLX    memclr_1                            ; Branch with Link and Exchange (immediate address)
 
−
ROM:8F31C68E 008 10 BD                      POP    {R4,PC}                            ; Pop registers
 
−
ROM:8F31C68E                ; End of function pcap_init
 
−
ROM:8F31C68E
 
 
</syntaxhighlight>
 
</syntaxhighlight>

Revision as of 07:03, 15 January 2012

it is a Motorola's name of Power Manager chip (TWL5030 for our phones)

Block Diagram

TPS65950 Block Diagram.png

Debugging

Code Samples

  1. uint16_t cpcap_regacc_read(uint16_t reg, uint16_t *buf, uint16_t mask)
  2. {
  3.   treg = (reg << 19) >> 1;
  4.   spi_send_ORR(0, 0);
  5.   spi_read_write_2(0, 0, treg, buf);
  6.   spi_send_BIC(0, 0);
  7.   *buf &= mask;
  8.   return *buf;
  9. }
  10.  
  11. uint16_t cpcap_regacc_write(uint16_t reg, uint16_t data, uint16_t mask)
  12. {
  13.   uint16_t buf = 0;
  14.   uint16_t treg;
  15.  
  16.   cpcap_regacc_read(reg, &buf, 65535);
  17.   buf &= ~mask;
  18.   __asm { UBFX.W  treg, reg, #0, #0xD ; Unsigned Bit Field Extract }
  19.   treg = (treg << 18) | 0x80000000 | (uint16_t)(data & mask | (uint16_t)buf);
  20.   spi_send_ORR(0, 0);
  21.   spi_read_write_2(0, 0, treg, buf);
  22.   spi_send_BIC(0, 0);
  23.   return buf;
  24. }
  25.  
  26. void cpcap_init_chain()
  27. {
  28.   cpcap_regacc_write(387, 25656, 0xFFFF);
  29.   cpcap_regacc_write(394, 40, 0xFFFF);
  30.   cpcap_regacc_write(12, 257, 0xFFFF);
  31.   cpcap_regacc_write(391, 1337, 0xFFFF);
  32.   cpcap_regacc_write(385, 513, 0xFFFF);
  33.   cpcap_regacc_write(386, 196, 0xFFFF);
  34.   cpcap_regacc_write(397, 19, 0xFFFF);
  35.   delay(1);
  36.   cpcap_regacc_write(411, 324, 0xFFFF);
  37.   cpcap_regacc_write(412, 41, 0xFFFF;
  38.   cpcap_regacc_write(413, 41, 0xFFFF);
  39.   cpcap_regacc_write(768, 4096, 0xFFFF);
  40.   cpcap_regacc_write(769, 16755, 0xFF7F);
  41.   cpcap_regacc_write(896, 4097, 0xFFFF);
  42.   cpcap_regacc_write(897, 49184, 0xFFFF);
  43.   cpcap_regacc_write(898, 15615, 0xFFFF);
  44.   cpcap_regacc_write(1024, 16383, 0xFFFF);
  45.   cpcap_regacc_write(7936, 21577, 0xFFFF);
  46.   cpcap_regacc_write(7970, 2720, 0xFFFF);
  47.   cpcap_regacc_write(7936, 0, 0xFFFF);
  48.   cpcap_regacc_write(384, 56068, 0xFFFF);
  49. }
  50.  
  51. void cpcap_reset_chain()
  52. {
  53.   cpcap_regacc_write(384, 56084, 0xFFFF);
  54.   cpcap_regacc_write(385, 513, 0xFFFF);
  55.   cpcap_regacc_write(386, 196, 0xFFFF);
  56.   cpcap_regacc_write(387, 25652, 0xFFFF);
  57.   cpcap_regacc_write(388, 15380, 0xFFFF);
  58.   cpcap_regacc_write(389, 25652, 0xFFFF);
  59.   cpcap_regacc_write(390, 15380, 0xFFFF);
  60.   cpcap_regacc_write(391, 1337, 0xFFFF);
  61.   cpcap_regacc_write(392, 18740, 0xFFFF);
  62.   cpcap_regacc_write(394, 0, 0xFFFF);
  63.   cpcap_regacc_write(395, 0, 0xFFFF);
  64.   cpcap_regacc_write(396, 0, 0xFFFF);
  65.   cpcap_regacc_write(398, 0, 0xFFFF);
  66.   cpcap_regacc_write(399, 0, 0xFFFF);
  67.   cpcap_regacc_write(400, 0, 0xFFFF);
  68.   cpcap_regacc_write(401, 0, 0xFFFF);
  69.   cpcap_regacc_write(402, 0, 0xFFFF);
  70.   cpcap_regacc_write(403, 91, 0xFFFF);
  71.   cpcap_regacc_write(404, 0, 0xFFFF);
  72.   cpcap_regacc_write(405, 0, 0xFFFF);
  73.   cpcap_regacc_write(406, 41, 0xFFFF);
  74.   cpcap_regacc_write(407, 0, 0xFFFF);
  75.   cpcap_regacc_write(408, 0, 0xFFFF);
  76.   cpcap_regacc_write(409, 0, 0xFFFF);
  77.   cpcap_regacc_write(410, 0, 0xFFFF);
  78.   cpcap_regacc_write(411, 0, 0xFFFF);
  79.   cpcap_regacc_write(412, 41, 0xFFFF);
  80.   cpcap_regacc_write(413, 41, 0xFFFF);
  81.   cpcap_regacc_write(512, 0, 0xFFFF);
  82.   cpcap_regacc_write(1024, 0, 0xFFFF);
  83.   cpcap_regacc_write(1025, 0, 0xFFFF);
  84.   cpcap_regacc_write(1026, 0, 0xFFFF);
  85. }
  86.  
  87. void cpcap_init()
  88. {
  89.   log_write("\r\n************* \r\n");
  90.   log_write("CPCAP_init( ) \r\n");
  91.   log_write("************* \r\n");
  92.   spi_read_write_3();
  93.   cpcap_check_ULPI_and_VBUS();
  94.   cpcap_init_chain();
  95.   memclr(*(0x8FB52188), 0x80);
  96. }
Retrieved from "http://droid-developers.org/index.php?title=CPCAP&oldid=1274"