Display Subsystem

From MILEDROPEDIA
Jump to: navigation, search

Display SubSystem

Milestone uses Active TFT LCD with 24 bits per pixel of color and 480 x 854 resolution. It's connected to DSI PLL (serial) controller of OMAP3430. LCD has internal memory which should be updated by CPU request.

How it works

Screen image sits in system RAM (SDRAM) and DISPC_GFX_BAi registers points to address of start of this area. Other DISPC_GFX_x registers should be configure appropriately for LCD also. When you need to refresh LCD content, SDRAM should be copied to LCD over DSI protocol. Currently, on Android 2.1 it's configured to send data over DSI Virtual Channel number 1 (VC1) in Command mode (0x0). So VC0 gets data from L4 interconnection and VC1 gets data from DISPC.

How to update LCD content:

  • Enable DSS clocks (dss_ick, dss1_alwon_fck, dss2_alwon_fck, dss_tv_fck, dss_96m_fck)
  • Send 1230187 to DSI_VC1_TE register
  • Send (0x39 | 2881 << 8) to DSI_VC1_LONG_PACKET_HEADER  ; DSI_DT_DCS_LONG_WRITE command + packet length
  • Set bit TE_START to DSI_VC1_TE ; It strange: it's 17 bit in documentation, but 31 bit in driver...
  • Set Slave Idle Mode in DISPC_SYSCONFIG to No Idle mode (0x1)
  • Set bit LCDENABLE in DISPC_CONTROL.

Now DISPC should start to send data to DSI controller in appropriate sequence and DSI sent it to LCD.

BUG: Current way can update LCD only one time, so should be researched more...

Information from mbm

Invalid language.

You need to specify a language like this: <source lang="html4strict">...</source>

Supported languages for syntax highlighting:

4cs, 6502acme, 6502kickass, 6502tasm, 68000devpac, abap, actionscript, actionscript3, ada, algol68, apache, applescript, apt_sources, arm, asm, asp, asymptote, autoconf, autohotkey, autoit, avisynth, awk, bascomavr, bash, basic4gl, bf, bibtex, blitzbasic, bnf, boo, c, c_loadrunner, c_mac, caddcl, cadlisp, cfdg, cfm, chaiscript, cil, clojure, cmake, cobol, coffeescript, cpp, cpp-qt, csharp, css, cuesheet, d, dcl, dcpu16, dcs, delphi, diff, div, dos, dot, e, ecmascript, eiffel, email, epc, erlang, euphoria, f1, falcon, fo, fortran, freebasic, freeswitch, fsharp, gambas, gdb, genero, genie, gettext, glsl, gml, gnuplot, go, groovy, gwbasic, haskell, haxe, hicest, hq9plus, html4strict, html5, icon, idl, ini, inno, intercal, io, j, java, java5, javascript, jquery, kixtart, klonec, klonecpp, latex, lb, ldif, lisp, llvm, locobasic, logtalk, lolcode, lotusformulas, lotusscript, lscript, lsl2, lua, m68k, magiksf, make, mapbasic, matlab, mirc, mmix, modula2, modula3, mpasm, mxml, mysql, nagios, netrexx, newlisp, nsis, oberon2, objc, objeck, ocaml, ocaml-brief, octave, oobas, oorexx, oracle11, oracle8, oxygene, oz, parasail, parigp, pascal, pcre, per, perl, perl6, pf, php, php-brief, pic16, pike, pixelbender, pli, plsql, postgresql, povray, powerbuilder, powershell, proftpd, progress, prolog, properties, providex, purebasic, pycon, pys60, python, q, qbasic, rails, rebol, reg, rexx, robots, rpmspec, rsplus, ruby, sas, scala, scheme, scilab, sdlbasic, smalltalk, smarty, spark, sparql, sql, stonescript, systemverilog, tcl, teraterm, text, thinbasic, tsql, typoscript, unicon, upc, urbi, uscript, vala, vb, vbnet, vedit, verilog, vhdl, vim, visualfoxpro, visualprolog, whitespace, whois, winbatch, xbasic, xml, xorg_conf, xpp, yaml, z80, zxbasic


 ; =============== S U B R O U T I N E =======================================
ROM:8F324D52
ROM:8F324D52
ROM:8F324D52                 ; int __fastcall display_cursor_set(int x, int y)
ROM:8F324D52                 display_cursor_set                                          ; CODE XREF: display_draw_text+18
ROM:8F324D52 000 C2 00                       LSLS    R2, R0, #3                          ; Logical Shift Left
ROM:8F324D54 000 AC 4B                       LDR     R3, =0x8F32D868                     ; Load from Memory
ROM:8F324D56 000 24 33                       ADDS    R3, #(cur_x - 0x8F32D868)           ; Rd = Op1 + Op2
ROM:8F324D58 000 1A 60                       STR     R2, [R3]                            ; Store to Memory
ROM:8F324D5A 000 0B 22                       MOVS    R2, #0xB                            ; Rd = Op2
ROM:8F324D5C 000 4A 43                       MULS    R2, R1                              ; Multiply
ROM:8F324D5E 000 1B 1D                       ADDS    R3, R3, #(cur_y - 0x8F32D88C)       ; Rd = Op1 + Op2
ROM:8F324D60 000 1A 60                       STR     R2, [R3]                            ; Store to Memory
ROM:8F324D62 000 70 47                       BX      LR                                  ; Branch to/from Thumb mode
ROM:8F324D62                 ; End of function display_cursor_set
ROM:8F324D62
ROM:8F324D64                 ; ---------------------------------------------------------------------------
ROM:8F324D64 2D E9 F0 41                     PUSH.W  {R4-R8,LR}                          ; Push registers
ROM:8F324D68 20 28                           CMP     R0, #0x20                           ; Set cond. codes on Op1 - Op2
ROM:8F324D6A 1D DB                           BLT     loc_8F324DA8                        ; Branch
ROM:8F324D6C 7E 28                           CMP     R0, #0x7E                           ; Set cond. codes on Op1 - Op2
ROM:8F324D6E 1B DC                           BGT     loc_8F324DA8                        ; Branch
ROM:8F324D70 01 22                           MOVS    R2, #1                              ; Rd = Op2
ROM:8F324D72 A0 F1 20 08                     SUB.W   R8, R0, #0x20                       ; Rd = Op1 - Op2
ROM:8F324D76 4F EA C8 08                     MOV.W   R8, R8,LSL#3                        ; Rd = Op2
ROM:8F324D7A C8 EB C8 07                     RSB.W   R7, R8, R8,LSL#3                    ; Rd = Op2 - Op1
ROM:8F324D7E 4F EA E7 78                     MOV.W   R8, R7,ASR#31                       ; Rd = Op2
ROM:8F324D82 07 EB 58 78                     ADD.W   R8, R7, R8,LSR#29                   ; Rd = Op1 + Op2
ROM:8F324D86 4F EA E8 03                     MOV.W   R3, R8,ASR#3                        ; Rd = Op2
ROM:8F324D8A A0 F1 20 08                     SUB.W   R8, R0, #0x20                       ; Rd = Op1 - Op2
ROM:8F324D8E 4F EA C8 08                     MOV.W   R8, R8,LSL#3                        ; Rd = Op2
ROM:8F324D92 C8 EB C8 07                     RSB.W   R7, R8, R8,LSL#3                    ; Rd = Op2 - Op1
ROM:8F324D96 4F EA E7 78                     MOV.W   R8, R7,ASR#31                       ; Rd = Op2
ROM:8F324D9A 07 EB 58 78                     ADD.W   R8, R7, R8,LSR#29                   ; Rd = Op1 + Op2
ROM:8F324D9E 4F EA E8 08                     MOV.W   R8, R8,ASR#3                        ; Rd = Op2
ROM:8F324DA2 A7 EB C8 04                     SUB.W   R4, R7, R8,LSL#3                    ; Rd = Op1 - Op2
ROM:8F324DA6 02 E0                           B       loc_8F324DAE                        ; Branch
ROM:8F324DA8                 ; ---------------------------------------------------------------------------
ROM:8F324DA8
ROM:8F324DA8                 loc_8F324DA8                                                ; CODE XREF: ROM:8F324D6A
ROM:8F324DA8                                                                             ; ROM:8F324D6E
ROM:8F324DA8 00 22                           MOVS    R2, #0                              ; Rd = Op2
ROM:8F324DAA 00 23                           MOVS    R3, #0                              ; Rd = Op2
ROM:8F324DAC 00 24                           MOVS    R4, #0                              ; Rd = Op2
ROM:8F324DAE
ROM:8F324DAE                 loc_8F324DAE                                                ; CODE XREF: ROM:8F324DA6
ROM:8F324DAE 96 4F                           LDR     R7, =fb_addr_0                      ; Load from Memory
ROM:8F324DB0 1C 37                           ADDS    R7, #0x1C                           ; Rd = Op1 + Op2
ROM:8F324DB2 3F 68                           LDR     R7, [R7]                            ; Load from Memory
ROM:8F324DB4 DF F8 50 82                     LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324DB8 08 F1 24 08                     ADD.W   R8, R8, #0x24                       ; Rd = Op1 + Op2
ROM:8F324DBC D8 F8 00 80                     LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324DC0 07 EB 08 05                     ADD.W   R5, R7, R8                          ; Rd = Op1 + Op2
ROM:8F324DC4 90 4F                           LDR     R7, =fb_addr_0                      ; Load from Memory
ROM:8F324DC6 20 37                           ADDS    R7, #0x20                           ; Rd = Op1 + Op2
ROM:8F324DC8 3F 68                           LDR     R7, [R7]                            ; Load from Memory
ROM:8F324DCA DF F8 3C 82                     LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324DCE 08 F1 28 08                     ADD.W   R8, R8, #0x28                       ; Rd = Op1 + Op2
ROM:8F324DD2 D8 F8 00 80                     LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324DD6 07 EB 08 06                     ADD.W   R6, R7, R8                          ; Rd = Op1 + Op2
ROM:8F324DDA 4F F0 00 0E                     MOV.W   LR, #0                              ; Rd = Op2
ROM:8F324DDE 6F E0                           B       loc_8F324EC0                        ; Branch
ROM:8F324DE0                 ; ---------------------------------------------------------------------------
ROM:8F324DE0
ROM:8F324DE0                 loc_8F324DE0                                                ; CODE XREF: ROM:8F324EC4
ROM:8F324DE0 4F F0 00 0C                     MOV.W   R12, #0                             ; Rd = Op2
ROM:8F324DE4 67 E0                           B       loc_8F324EB6                        ; Branch
ROM:8F324DE6                 ; ---------------------------------------------------------------------------
ROM:8F324DE6
ROM:8F324DE6                 loc_8F324DE6                                                ; CODE XREF: ROM:8F324EBA
ROM:8F324DE6 06 EB 0E 07                     ADD.W   R7, R6, LR                          ; Rd = Op1 + Op2
ROM:8F324DEA DF F8 1C 82                     LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324DEE 08 F1 14 08                     ADD.W   R8, R8, #0x14                       ; Rd = Op1 + Op2
ROM:8F324DF2 D8 F8 00 80                     LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324DF6 47 45                           CMP     R7, R8                              ; Set cond. codes on Op1 - Op2
ROM:8F324DF8 4E DB                           BLT     loc_8F324E98                        ; Branch
ROM:8F324DFA 06 EB 0E 07                     ADD.W   R7, R6, LR                          ; Rd = Op1 + Op2
ROM:8F324DFE DF F8 08 82                     LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324E02 08 F1 18 08                     ADD.W   R8, R8, #0x18                       ; Rd = Op1 + Op2
ROM:8F324E06 D8 F8 00 80                     LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324E0A 47 45                           CMP     R7, R8                              ; Set cond. codes on Op1 - Op2
ROM:8F324E0C 44 DC                           BGT     loc_8F324E98                        ; Branch
ROM:8F324E0E 05 EB 0C 07                     ADD.W   R7, R5, R12                         ; Rd = Op1 + Op2
ROM:8F324E12 DF F8 F4 81                     LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324E16 08 F1 0C 08                     ADD.W   R8, R8, #0xC                        ; Rd = Op1 + Op2
ROM:8F324E1A D8 F8 00 80                     LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324E1E 47 45                           CMP     R7, R8                              ; Set cond. codes on Op1 - Op2
ROM:8F324E20 3A DB                           BLT     loc_8F324E98                        ; Branch
ROM:8F324E22 05 EB 0C 07                     ADD.W   R7, R5, R12                         ; Rd = Op1 + Op2
ROM:8F324E26 DF F8 E0 81                     LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324E2A 08 F1 10 08                     ADD.W   R8, R8, #0x10                       ; Rd = Op1 + Op2
ROM:8F324E2E D8 F8 00 80                     LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324E32 47 45                           CMP     R7, R8                              ; Set cond. codes on Op1 - Op2
ROM:8F324E34 30 DC                           BGT     loc_8F324E98                        ; Branch
ROM:8F324E36 06 EB 0E 07                     ADD.W   R7, R6, LR                          ; Rd = Op1 + Op2
ROM:8F324E3A C7 EB 07 17                     RSB.W   R7, R7, R7,LSL#4                    ; Rd = Op2 - Op1
ROM:8F324E3E 05 EB 47 17                     ADD.W   R7, R5, R7,LSL#5                    ; Rd = Op1 + Op2
ROM:8F324E42 67 44                           ADD     R7, R12                             ; Rd = Op1 + Op2
ROM:8F324E44 DF F8 C0 81                     LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324E48 D8 F8 00 80                     LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324E4C 08 EB 47 01                     ADD.W   R1, R8, R7,LSL#1                    ; Rd = Op1 + Op2
ROM:8F324E50 C2 B1                           CBZ     R2, loc_8F324E84                    ; Compare and Branch on Zero
ROM:8F324E52 6F 4F                           LDR     R7, =font                           ; Load from Memory
ROM:8F324E54 17 F8 03 80                     LDRB.W  R8, [R7,R3]                         ; Load from Memory
ROM:8F324E58 80 27                           MOVS    R7, #0x80                           ; Rd = Op2
ROM:8F324E5A 27 41                           ASRS    R7, R4                              ; Arithmetic Shift Right
ROM:8F324E5C 18 EA 07 0F                     TST.W   R8, R7                              ; Set cond. codes on Op1 & Op2
ROM:8F324E60 10 D0                           BEQ     loc_8F324E84                        ; Branch
ROM:8F324E62 BC F1 07 0F                     CMP.W   R12, #7                             ; Set cond. codes on Op1 - Op2
ROM:8F324E66 0D DA                           BGE     loc_8F324E84                        ; Branch
ROM:8F324E68 BE F1 08 0F                     CMP.W   LR, #8                              ; Set cond. codes on Op1 - Op2
ROM:8F324E6C 0A DA                           BGE     loc_8F324E84                        ; Branch
ROM:8F324E6E 66 4F                           LDR     R7, =fb_addr_0                      ; Load from Memory
ROM:8F324E70 3F 1D                           ADDS    R7, R7, #4                          ; Rd = Op1 + Op2
ROM:8F324E72 3F 68                           LDR     R7, [R7]                            ; Load from Memory
ROM:8F324E74 17 F0 00 4F                     TST.W   R7, #0x80000000                     ; Set cond. codes on Op1 & Op2
ROM:8F324E78 0E D1                           BNE     loc_8F324E98                        ; Branch
ROM:8F324E7A 63 4F                           LDR     R7, =fb_addr_0                      ; Load from Memory
ROM:8F324E7C 3F 1D                           ADDS    R7, R7, #4                          ; Rd = Op1 + Op2
ROM:8F324E7E 3F 68                           LDR     R7, [R7]                            ; Load from Memory
ROM:8F324E80 0F 80                           STRH    R7, [R1]                            ; Store to Memory
ROM:8F324E82 09 E0                           B       loc_8F324E98                        ; Branch
ROM:8F324E84                 ; ---------------------------------------------------------------------------
ROM:8F324E84
ROM:8F324E84                 loc_8F324E84                                                ; CODE XREF: ROM:8F324E50
ROM:8F324E84                                                                             ; ROM:8F324E60 ...
ROM:8F324E84 60 4F                           LDR     R7, =fb_addr_0                      ; Load from Memory
ROM:8F324E86 08 37                           ADDS    R7, #8                              ; Rd = Op1 + Op2
ROM:8F324E88 3F 68                           LDR     R7, [R7]                            ; Load from Memory
ROM:8F324E8A 17 F0 00 4F                     TST.W   R7, #0x80000000                     ; Set cond. codes on Op1 & Op2
ROM:8F324E8E 03 D1                           BNE     loc_8F324E98                        ; Branch
ROM:8F324E90 5D 4F                           LDR     R7, =fb_addr_0                      ; Load from Memory
ROM:8F324E92 08 37                           ADDS    R7, #8                              ; Rd = Op1 + Op2
ROM:8F324E94 3F 68                           LDR     R7, [R7]                            ; Load from Memory
ROM:8F324E96 0F 80                           STRH    R7, [R1]                            ; Store to Memory
ROM:8F324E98
ROM:8F324E98                 loc_8F324E98                                                ; CODE XREF: ROM:8F324DF8
ROM:8F324E98                                                                             ; ROM:8F324E0C ...
ROM:8F324E98 5A B1                           CBZ     R2, loc_8F324EB2                    ; Compare and Branch on Zero
ROM:8F324E9A BC F1 07 0F                     CMP.W   R12, #7                             ; Set cond. codes on Op1 - Op2
ROM:8F324E9E 08 DA                           BGE     loc_8F324EB2                        ; Branch
ROM:8F324EA0 BE F1 08 0F                     CMP.W   LR, #8                              ; Set cond. codes on Op1 - Op2
ROM:8F324EA4 05 DA                           BGE     loc_8F324EB2                        ; Branch
ROM:8F324EA6 67 1C                           ADDS    R7, R4, #1                          ; Rd = Op1 + Op2
ROM:8F324EA8 3C 46                           MOV     R4, R7                              ; Rd = Op2
ROM:8F324EAA 08 2F                           CMP     R7, #8                              ; Set cond. codes on Op1 - Op2
ROM:8F324EAC 01 DB                           BLT     loc_8F324EB2                        ; Branch
ROM:8F324EAE 00 24                           MOVS    R4, #0                              ; Rd = Op2
ROM:8F324EB0 5B 1C                           ADDS    R3, R3, #1                          ; Rd = Op1 + Op2
ROM:8F324EB2
ROM:8F324EB2                 loc_8F324EB2                                                ; CODE XREF: ROM:loc_8F324E98
ROM:8F324EB2                                                                             ; ROM:8F324E9E ...
ROM:8F324EB2 0C F1 01 0C                     ADD.W   R12, R12, #1                        ; Rd = Op1 + Op2
ROM:8F324EB6
ROM:8F324EB6                 loc_8F324EB6                                                ; CODE XREF: ROM:8F324DE4
ROM:8F324EB6 BC F1 08 0F                     CMP.W   R12, #8                             ; Set cond. codes on Op1 - Op2
ROM:8F324EBA 94 DB                           BLT     loc_8F324DE6                        ; Branch
ROM:8F324EBC 0E F1 01 0E                     ADD.W   LR, LR, #1                          ; Rd = Op1 + Op2
ROM:8F324EC0
ROM:8F324EC0                 loc_8F324EC0                                                ; CODE XREF: ROM:8F324DDE
ROM:8F324EC0 BE F1 0B 0F                     CMP.W   LR, #0xB                            ; Set cond. codes on Op1 - Op2
ROM:8F324EC4 8C DB                           BLT     loc_8F324DE0                        ; Branch
ROM:8F324EC6 BD E8 F0 81                     POP.W   {R4-R8,PC}                          ; Pop registers
ROM:8F324ECA
ROM:8F324ECA                 ; =============== S U B R O U T I N E =======================================
ROM:8F324ECA
ROM:8F324ECA
ROM:8F324ECA                 ; int __fastcall display_draw_symbol(char sym)
ROM:8F324ECA                 display_draw_symbol                                         ; CODE XREF: display_put_char+24
ROM:8F324ECA 000 2D E9 F0 43                 PUSH.W  {R4-R9,LR}                          ; Push registers
ROM:8F324ECE 01C 20 28                       CMP     R0, #0x20                           ; Set cond. codes on Op1 - Op2
ROM:8F324ED0 01C 1D DB                       BLT     loc_8F324F0E                        ; Branch
ROM:8F324ED2 01C 7E 28                       CMP     R0, #0x7E                           ; Set cond. codes on Op1 - Op2
ROM:8F324ED4 01C 1B DC                       BGT     loc_8F324F0E                        ; Branch
ROM:8F324ED6 01C 01 22                       MOVS    R2, #1                              ; Rd = Op2
ROM:8F324ED8 01C A0 F1 20 08                 SUB.W   R8, R0, #0x20                       ; Rd = Op1 - Op2
ROM:8F324EDC 01C 4F EA C8 08                 MOV.W   R8, R8,LSL#3                        ; Rd = Op2
ROM:8F324EE0 01C C8 EB C8 0E                 RSB.W   LR, R8, R8,LSL#3                    ; Rd = Op2 - Op1
ROM:8F324EE4 01C 4F EA EE 78                 MOV.W   R8, LR,ASR#31                       ; Rd = Op2
ROM:8F324EE8 01C 0E EB 58 78                 ADD.W   R8, LR, R8,LSR#29                   ; Rd = Op1 + Op2
ROM:8F324EEC 01C 4F EA E8 03                 MOV.W   R3, R8,ASR#3                        ; Rd = Op2
ROM:8F324EF0 01C A0 F1 20 08                 SUB.W   R8, R0, #0x20                       ; Rd = Op1 - Op2
ROM:8F324EF4 01C 4F EA C8 08                 MOV.W   R8, R8,LSL#3                        ; Rd = Op2
ROM:8F324EF8 01C C8 EB C8 0E                 RSB.W   LR, R8, R8,LSL#3                    ; Rd = Op2 - Op1
ROM:8F324EFC 01C 4F EA EE 78                 MOV.W   R8, LR,ASR#31                       ; Rd = Op2
ROM:8F324F00 01C 0E EB 58 78                 ADD.W   R8, LR, R8,LSR#29                   ; Rd = Op1 + Op2
ROM:8F324F04 01C 4F EA E8 08                 MOV.W   R8, R8,ASR#3                        ; Rd = Op2
ROM:8F324F08 01C AE EB C8 04                 SUB.W   R4, LR, R8,LSL#3                    ; Rd = Op1 - Op2
ROM:8F324F0C 01C 02 E0                       B       loc_8F324F14                        ; Branch
ROM:8F324F0E                 ; ---------------------------------------------------------------------------
ROM:8F324F0E
ROM:8F324F0E                 loc_8F324F0E                                                ; CODE XREF: display_draw_symbol+6
ROM:8F324F0E                                                                             ; display_draw_symbol+A
ROM:8F324F0E 01C 00 22                       MOVS    R2, #0                              ; Rd = Op2
ROM:8F324F10 01C 00 23                       MOVS    R3, #0                              ; Rd = Op2
ROM:8F324F12 01C 00 24                       MOVS    R4, #0                              ; Rd = Op2
ROM:8F324F14
ROM:8F324F14                 loc_8F324F14                                                ; CODE XREF: display_draw_symbol+42
ROM:8F324F14 01C DF F8 F0 E0                 LDR.W   LR, =fb_addr_0                      ; Load from Memory
ROM:8F324F18 01C 0E F1 1C 0E                 ADD.W   LR, LR, #(cur_x - 0x8F32D870)       ; Rd = Op1 + Op2
ROM:8F324F1C 01C DE F8 00 E0                 LDR.W   LR, [LR]                            ; Load from Memory
ROM:8F324F20 01C DF F8 E4 80                 LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324F24 01C 08 F1 24 08                 ADD.W   R8, R8, #(fb_addr - 0x8F32D870)     ; Rd = Op1 + Op2
ROM:8F324F28 01C D8 F8 00 80                 LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324F2C 01C 0E EB 08 05                 ADD.W   R5, LR, R8                          ; Rd = Op1 + Op2
ROM:8F324F30 01C DF F8 D4 E0                 LDR.W   LR, =fb_addr_0                      ; Load from Memory
ROM:8F324F34 01C 0E F1 20 0E                 ADD.W   LR, LR, #(cur_y - 0x8F32D870)       ; Rd = Op1 + Op2
ROM:8F324F38 01C DE F8 00 E0                 LDR.W   LR, [LR]                            ; Load from Memory
ROM:8F324F3C 01C DF F8 C8 80                 LDR.W   R8, =fb_addr_0                      ; Load from Memory
ROM:8F324F40 01C 08 F1 28 08                 ADD.W   R8, R8, #(dword_8F32D898 - 0x8F32D870) ; Rd = Op1 + Op2
ROM:8F324F44 01C D8 F8 00 80                 LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324F48 01C 0E EB 08 06                 ADD.W   R6, LR, R8                          ; Rd = Op1 + Op2
ROM:8F324F4C 01C 4F F0 00 0C                 MOV.W   R12, #0                             ; Rd = Op2
ROM:8F324F50 01C BA E0                       B       loc_8F3250C8                        ; Branch
ROM:8F324F52                 ; ---------------------------------------------------------------------------
ROM:8F324F52
ROM:8F324F52                 loc_8F324F52                                                ; CODE XREF: display_draw_symbol+202
ROM:8F324F52 01C 00 27                       MOVS    R7, #0                              ; Rd = Op2
ROM:8F324F54 01C B3 E0                       B       loc_8F3250BE                        ; Branch
ROM:8F324F56                 ; ---------------------------------------------------------------------------
ROM:8F324F56
ROM:8F324F56                 loc_8F324F56                                                ; CODE XREF: display_draw_symbol+1F6
ROM:8F324F56 01C 06 EB 0C 0E                 ADD.W   LR, R6, R12                         ; Rd = Op1 + Op2
ROM:8F324F5A 01C DF F8 AC 80                 LDR.W   R8, =0x8F32D868                     ; Load from Memory
ROM:8F324F5E 01C 08 F1 14 08                 ADD.W   R8, R8, #(dword_8F32D884 - 0x8F32D870) ; Rd = Op1 + Op2
ROM:8F324F62 01C D8 F8 00 80                 LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324F66 01C C6 45                       CMP     LR, R8                              ; Set cond. codes on Op1 - Op2
ROM:8F324F68
ROM:8F324F68                 loc_8F324F68                                                ; CODE XREF: display_draw_symbol+C6
ROM:8F324F68 01C 72 DB                       BLT     loc_8F325050                        ; Branch
ROM:8F324F6A 01C 06 EB 0C 0E                 ADD.W   LR, R6, R12                         ; Rd = Op1 + Op2
ROM:8F324F6E 01C DF F8 98 80                 LDR.W   R8, =0x8F32D868                     ; Load from Memory
ROM:8F324F72 01C 08 F1 18 08                 ADD.W   R8, R8, #(font_height - 0x8F32D870) ; Rd = Op1 + Op2
ROM:8F324F76 01C D8 F8 00 80                 LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324F7A 01C C6 45                       CMP     LR, R8                              ; Set cond. codes on Op1 - Op2
ROM:8F324F7C 01C 68 DC                       BGT     loc_8F325050                        ; Branch
ROM:8F324F7E 01C 05 EB 07 0E                 ADD.W   LR, R5, R7                          ; Rd = Op1 + Op2
ROM:8F324F82 01C DF F8 84 80                 LDR.W   R8, =0x8F32D868                     ; Load from Memory
ROM:8F324F86 01C 08 F1 0C 08                 ADD.W   R8, R8, #(dword_8F32D87C - 0x8F32D870) ; Rd = Op1 + Op2
ROM:8F324F8A 01C D8 F8 00 80                 LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324F8E 01C C6 45                       CMP     LR, R8                              ; Set cond. codes on Op1 - Op2
ROM:8F324F90 01C EA DB                       BLT     loc_8F324F68                        ; Branch
ROM:8F324F92 01C 05 EB 07 0E                 ADD.W   LR, R5, R7                          ; Rd = Op1 + Op2
ROM:8F324F96 01C DF F8 70 80                 LDR.W   R8, =0x8F32D868                     ; Load from Memory
ROM:8F324F9A 01C 08 F1 10 08                 ADD.W   R8, R8, #(lcd_height - 0x8F32D870)  ; Rd = Op1 + Op2
ROM:8F324F9E 01C D8 F8 00 80                 LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324FA2 01C C6 45                       CMP     LR, R8                              ; Set cond. codes on Op1 - Op2
ROM:8F324FA4 01C 7C DC                       BGT     loc_8F3250A0                        ; Branch
ROM:8F324FA6 01C 06 EB 0C 0E                 ADD.W   LR, R6, R12                         ; Rd = Op1 + Op2
ROM:8F324FAA 01C 4F F4 F0 78                 MOV.W   R8, #480                            ; Rd = Op2
ROM:8F324FAE 01C 0E FB 08 FE                 MUL.W   LR, LR, R8                          ; Multiply
ROM:8F324FB2 01C 05 EB 8E 0E                 ADD.W   LR, R5, LR,LSL#2                    ; Rd = Op1 + Op2
ROM:8F324FB6 01C BE 44                       ADD     LR, R7                              ; Rd = Op1 + Op2
ROM:8F324FB8 01C DF F8 58 80                 LDR.W   R8, =fb_addr                        ; Load from Memory
ROM:8F324FBC 01C D8 F8 00 80                 LDR.W   R8, [R8]                            ; Load from Memory
ROM:8F324FC0 01C 4F F0 03 09                 MOV.W   R9, #3                              ; Rd = Op2
ROM:8F324FC4 01C 09 FB 0E 81                 MLA.W   R1, R9, LR, R8                      ; Multiply-Accumulate
ROM:8F324FC8 01C 00 2A                       CMP     R2, #0                              ; Set cond. codes on Op1 - Op2
ROM:8F324FCA 01C 42 D0                       BEQ     loc_8F325052                        ; Branch
ROM:8F324FCC 01C DF F8 40 E0                 LDR.W   LR, =font                           ; Load from Memory
ROM:8F324FD0 01C 1E F8 03 80                 LDRB.W  R8, [LR,R3]                         ; Load from Memory
ROM:8F324FD4 01C 4F F0 80 0E                 MOV.W   LR, #0x80                           ; Rd = Op2
ROM:8F324FD8 01C 4E FA 04 FE                 ASR.W   LR, LR, R4                          ; Arithmetic Shift Right
ROM:8F324FDC 01C 18 EA 0E 0F                 TST.W   R8, LR                              ; Set cond. codes on Op1 & Op2
ROM:8F324FE0 01C 37 D0                       BEQ     loc_8F325052                        ; Branch
ROM:8F324FE2 01C 07 2F                       CMP     R7, #7                              ; Set cond. codes on Op1 - Op2
ROM:8F324FE4 01C 35 DA                       BGE     loc_8F325052                        ; Branch
ROM:8F324FE6 01C BC F1 08 0F                 CMP.W   R12, #8                             ; Set cond. codes on Op1 - Op2
ROM:8F324FEA 01C 32 DA                       BGE     loc_8F325052                        ; Branch
ROM:8F324FEC 01C DF F8 18 E0                 LDR.W   LR, =fb_addr_0                      ; Load from Memory
ROM:8F324FF0 01C 0E F1 04 0E                 ADD.W   LR, LR, #4                          ; Rd = Op1 + Op2
ROM:8F324FF4 01C DE F8 00 E0                 LDR.W   LR, [LR]                            ; Load from Memory
ROM:8F324FF8 01C 1E F0 00 4F                 TST.W   LR, #0x80000000                     ; Set cond. codes on Op1 & Op2
ROM:8F324FFC 01C 50 D1                       BNE     loc_8F3250A0                        ; Branch
ROM:8F324FFE 01C 4F F0 FF 0E                 MOV.W   LR, #0xFF                           ; Rd = Op2
ROM:8F325002 01C 81 F8 00 E0                 STRB.W  LR, [R1]                            ; Store to Memory
ROM:8F325006 01C 07 E0                       B       loc_8F325018                        ; Branch
ROM:8F325006                 ; ---------------------------------------------------------------------------
ROM:8F325008 01C 68 D8 32 8F off_8F325008    DCD fb_addr_0                               ; DATA XREF: ROM:8F324C08
ROM:8F325008 01C                                                                         ; ROM:8F324C2A ...
ROM:8F32500C 01C 40 41 06 00 dword_8F32500C  DCD 0x64140                                 ; DATA XREF: ROM:loc_8F324C3C
ROM:8F32500C 01C                                                                         ; sub_8F324C54:loc_8F324C74
ROM:8F325010 01C E8 CA 32 8F off_8F325010    DCD font                                    ; DATA XREF: ROM:8F324E52
ROM:8F325010 01C                                                                         ; display_draw_symbol+102
ROM:8F325014 01C 94 D8 32 8F off_8F325014    DCD fb_addr                                 ; DATA XREF: display_draw_symbol+EE
ROM:8F325018                 ; ---------------------------------------------------------------------------
ROM:8F325018
ROM:8F325018                 loc_8F325018                                                ; CODE XREF: display_draw_symbol+13C
ROM:8F325018 01C 81 F8 01 E0                 STRB.W  LR, [R1,#1]                         ; Store to Memory
ROM:8F32501C 01C 81 F8 02 E0                 STRB.W  LR, [R1,#2]                         ; Store to Memory
ROM:8F325020 01C 01 F5 B4 61                 ADD.W   R1, R1, #0x5A0                      ; Rd = Op1 + Op2
ROM:8F325024 01C 81 F8 00 E0                 STRB.W  LR, [R1]                            ; Store to Memory
ROM:8F325028 01C 81 F8 01 E0                 STRB.W  LR, [R1,#1]                         ; Store to Memory
ROM:8F32502C 01C 81 F8 02 E0                 STRB.W  LR, [R1,#2]                         ; Store to Memory
ROM:8F325030 01C 01 F5 B4 61                 ADD.W   R1, R1, #0x5A0                      ; Rd = Op1 + Op2
ROM:8F325034 01C 81 F8 00 E0                 STRB.W  LR, [R1]                            ; Store to Memory
ROM:8F325038 01C 81 F8 01 E0                 STRB.W  LR, [R1,#1]                         ; Store to Memory
ROM:8F32503C 01C 81 F8 02 E0                 STRB.W  LR, [R1,#2]                         ; Store to Memory
ROM:8F325040 01C 01 F5 B4 61                 ADD.W   R1, R1, #0x5A0                      ; Rd = Op1 + Op2
ROM:8F325044 01C 81 F8 00 E0                 STRB.W  LR, [R1]                            ; Store to Memory
ROM:8F325048 01C 81 F8 01 E0                 STRB.W  LR, [R1,#1]                         ; Store to Memory
ROM:8F32504C 01C 81 F8 02 E0                 STRB.W  LR, [R1,#2]                         ; Store to Memory
ROM:8F325050
ROM:8F325050                 loc_8F325050                                                ; CODE XREF: display_draw_symbol:loc_8F324F68
ROM:8F325050                                                                             ; display_draw_symbol+B2
ROM:8F325050 01C 26 E0                       B       loc_8F3250A0                        ; Branch
ROM:8F325052                 ; ---------------------------------------------------------------------------
ROM:8F325052
ROM:8F325052                 loc_8F325052                                                ; CODE XREF: display_draw_symbol+100
ROM:8F325052                                                                             ; display_draw_symbol+116 ...
ROM:8F325052 01C DF F8 28 E2                 LDR.W   LR, =dword_8F32D870                 ; Load from Memory
ROM:8F325056 01C DE F8 00 E0                 LDR.W   LR, [LR]                            ; Load from Memory
ROM:8F32505A 01C 1E F0 00 4F                 TST.W   LR, #0x80000000                     ; Set cond. codes on Op1 & Op2
ROM:8F32505E 01C 1F D1                       BNE     loc_8F3250A0                        ; Branch
ROM:8F325060 01C 4F F0 00 0E                 MOV.W   LR, #0                              ; Rd = Op2
ROM:8F325064 01C 81 F8 00 E0                 STRB.W  LR, [R1]                            ; Store to Memory
ROM:8F325068 01C 81 F8 01 E0                 STRB.W  LR, [R1,#1]                         ; Store to Memory
ROM:8F32506C 01C 81 F8 02 E0                 STRB.W  LR, [R1,#2]                         ; Store to Memory
ROM:8F325070 01C 01 F5 B4 61                 ADD.W   R1, R1, #0x5A0                      ; Rd = Op1 + Op2
ROM:8F325074 01C 81 F8 00 E0                 STRB.W  LR, [R1]                            ; Store to Memory
ROM:8F325078 01C 81 F8 01 E0                 STRB.W  LR, [R1,#1]                         ; Store to Memory
ROM:8F32507C 01C 81 F8 02 E0                 STRB.W  LR, [R1,#2]                         ; Store to Memory
ROM:8F325080 01C 01 F5 B4 61                 ADD.W   R1, R1, #0x5A0                      ; Rd = Op1 + Op2
ROM:8F325084 01C 81 F8 00 E0                 STRB.W  LR, [R1]                            ; Store to Memory
ROM:8F325088 01C 81 F8 01 E0                 STRB.W  LR, [R1,#1]                         ; Store to Memory
ROM:8F32508C 01C 81 F8 02 E0                 STRB.W  LR, [R1,#2]                         ; Store to Memory
ROM:8F325090 01C 01 F5 B4 61                 ADD.W   R1, R1, #0x5A0                      ; Rd = Op1 + Op2
ROM:8F325094 01C 81 F8 00 E0                 STRB.W  LR, [R1]                            ; Store to Memory
ROM:8F325098 01C 81 F8 01 E0                 STRB.W  LR, [R1,#1]                         ; Store to Memory
ROM:8F32509C 01C 81 F8 02 E0                 STRB.W  LR, [R1,#2]                         ; Store to Memory
ROM:8F3250A0
ROM:8F3250A0                 loc_8F3250A0                                                ; CODE XREF: display_draw_symbol+DA
ROM:8F3250A0                                                                             ; display_draw_symbol+132 ...
ROM:8F3250A0 01C 62 B1                       CBZ     R2, loc_8F3250BC                    ; Compare and Branch on Zero
ROM:8F3250A2 01C 07 2F                       CMP     R7, #7                              ; Set cond. codes on Op1 - Op2
ROM:8F3250A4 01C 0A DA                       BGE     loc_8F3250BC                        ; Branch
ROM:8F3250A6 01C BC F1 08 0F                 CMP.W   R12, #8                             ; Set cond. codes on Op1 - Op2
ROM:8F3250AA 01C 07 DA                       BGE     loc_8F3250BC                        ; Branch
ROM:8F3250AC 01C 04 F1 01 0E                 ADD.W   LR, R4, #1                          ; Rd = Op1 + Op2
ROM:8F3250B0 01C 74 46                       MOV     R4, LR                              ; Rd = Op2
ROM:8F3250B2 01C BE F1 08 0F                 CMP.W   LR, #8                              ; Set cond. codes on Op1 - Op2
ROM:8F3250B6 01C 01 DB                       BLT     loc_8F3250BC                        ; Branch
ROM:8F3250B8 01C 00 24                       MOVS    R4, #0                              ; Rd = Op2
ROM:8F3250BA 01C 5B 1C                       ADDS    R3, R3, #1                          ; Rd = Op1 + Op2
ROM:8F3250BC
ROM:8F3250BC                 loc_8F3250BC                                                ; CODE XREF: display_draw_symbol:loc_8F3250A0
ROM:8F3250BC                                                                             ; display_draw_symbol+1DA ...
ROM:8F3250BC 01C 7F 1C                       ADDS    R7, R7, #1                          ; Rd = Op1 + Op2
ROM:8F3250BE
ROM:8F3250BE                 loc_8F3250BE                                                ; CODE XREF: display_draw_symbol+8A
ROM:8F3250BE 01C 08 2F                       CMP     R7, #8                              ; Set cond. codes on Op1 - Op2
ROM:8F3250C0 01C FF F6 49 AF                 BLT.W   loc_8F324F56                        ; Branch
ROM:8F3250C4 01C 0C F1 01 0C                 ADD.W   R12, R12, #1                        ; Rd = Op1 + Op2
ROM:8F3250C8
ROM:8F3250C8                 loc_8F3250C8                                                ; CODE XREF: display_draw_symbol+86
ROM:8F3250C8 01C BC F1 0B 0F                 CMP.W   R12, #0xB                           ; Set cond. codes on Op1 - Op2
ROM:8F3250CC 01C FF F6 41 AF                 BLT.W   loc_8F324F52                        ; Branch
ROM:8F3250D0 01C BD E8 F0 83                 POP.W   {R4-R9,PC}                          ; Pop registers
ROM:8F3250D0 01C             ; End of function display_draw_symbol
ROM:8F3250D0
ROM:8F3250D4
ROM:8F3250D4                 ; =============== S U B R O U T I N E =======================================
ROM:8F3250D4
ROM:8F3250D4
ROM:8F3250D4                 ; int __fastcall display_put_char(char ch)
ROM:8F3250D4                 display_put_char                                            ; CODE XREF: display_put_string+8
ROM:8F3250D4 000 70 B5                       PUSH    {R4-R6,LR}                          ; Push registers
ROM:8F3250D6 010 04 46                       MOV     R4, R0                              ; Rd = Op2
ROM:8F3250D8 010 00 25                       MOVS    R5, #0                              ; Rd = Op2
ROM:8F3250DA 010 00 26                       MOVS    R6, #0                              ; Rd = Op2
ROM:8F3250DC 010 0A 2C                       CMP     R4, #0xA                            ; Set cond. codes on Op1 - Op2
ROM:8F3250DE 010 02 D1                       BNE     this_is_0xC                         ; Branch
ROM:8F3250E0 010 01 25                       MOVS    R5, #1                              ; Rd = Op2
ROM:8F3250E2 010 01 26                       MOVS    R6, #1                              ; Rd = Op2
ROM:8F3250E4 010 2F E0                       B       nl_cr                               ; Branch
ROM:8F3250E6                 ; ---------------------------------------------------------------------------
ROM:8F3250E6
ROM:8F3250E6                 this_is_0xC                                                 ; CODE XREF: display_put_char+A
ROM:8F3250E6 010 0C 2C                       CMP     R4, #0xC                            ; Set cond. codes on Op1 - Op2
ROM:8F3250E8 010 01 D1                       BNE     this_is_0xD                         ; Branch
ROM:8F3250EA 010 01 26                       MOVS    R6, #1                              ; Rd = Op2
ROM:8F3250EC 010 2B E0                       B       nl_cr                               ; Branch
ROM:8F3250EE                 ; ---------------------------------------------------------------------------
ROM:8F3250EE
ROM:8F3250EE                 this_is_0xD                                                 ; CODE XREF: display_put_char+14
ROM:8F3250EE 010 0D 2C                       CMP     R4, #0xD                            ; Set cond. codes on Op1 - Op2
ROM:8F3250F0 010 01 D1                       BNE     normal_char                         ; Branch
ROM:8F3250F2 010 01 25                       MOVS    R5, #1                              ; Rd = Op2
ROM:8F3250F4 010 27 E0                       B       nl_cr                               ; Branch
ROM:8F3250F6                 ; ---------------------------------------------------------------------------
ROM:8F3250F6
ROM:8F3250F6                 normal_char                                                 ; CODE XREF: display_put_char+1C
ROM:8F3250F6 010 20 46                       MOV     R0, R4                              ; sym
ROM:8F3250F8 010 FF F7 E7 FE                 BL      display_draw_symbol                 ; Branch with Link
ROM:8F3250FC 010 5F 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F3250FE 010 14 30                       ADDS    R0, #(dword_8F32D884 - 0x8F32D870)  ; Rd = Op1 + Op2
ROM:8F325100 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F325102 010 5E 49                       LDR     R1, =0x8F32D870                     ; Load from Memory
ROM:8F325104 010 1C 31                       ADDS    R1, #(cur_x - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F325106 010 09 68                       LDR     R1, [R1]                            ; Load from Memory
ROM:8F325108 010 01 44                       ADD     R1, R0                              ; Rd = Op1 + Op2
ROM:8F32510A 010 5C 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F32510C 010 08 30                       ADDS    R0, #(lcd_width - 0x8F32D870)       ; Rd = Op1 + Op2
ROM:8F32510E 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F325110 010 40 1C                       ADDS    R0, R0, #1                          ; Rd = Op1 + Op2
ROM:8F325112 010 81 42                       CMP     R1, R0                              ; Set cond. codes on Op1 - Op2
ROM:8F325114 010 10 DC                       BGT     loc_8F325138                        ; Branch
ROM:8F325116 010 59 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F325118 010 14 30                       ADDS    R0, #(dword_8F32D884 - 0x8F32D870)  ; Rd = Op1 + Op2
ROM:8F32511A 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F32511C 010 57 49                       LDR     R1, =0x8F32D870                     ; Load from Memory
ROM:8F32511E 010 1C 31                       ADDS    R1, #(cur_x - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F325120 010 09 68                       LDR     R1, [R1]                            ; Load from Memory
ROM:8F325122 010 01 44                       ADD     R1, R0                              ; Rd = Op1 + Op2
ROM:8F325124 010 0F 31                       ADDS    R1, #0xF                            ; Rd = Op1 + Op2
ROM:8F325126 010 55 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F325128 010 08 30                       ADDS    R0, #(lcd_width - 0x8F32D870)       ; Rd = Op1 + Op2
ROM:8F32512A 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F32512C 010 40 1C                       ADDS    R0, R0, #1                          ; Rd = Op1 + Op2
ROM:8F32512E 010 81 42                       CMP     R1, R0                              ; Set cond. codes on Op1 - Op2
ROM:8F325130 010 02 DD                       BLE     loc_8F325138                        ; Branch
ROM:8F325132 010 01 25                       MOVS    R5, #1                              ; Rd = Op2
ROM:8F325134 010 01 26                       MOVS    R6, #1                              ; Rd = Op2
ROM:8F325136 010 06 E0                       B       nl_cr                               ; Branch
ROM:8F325138                 ; ---------------------------------------------------------------------------
ROM:8F325138
ROM:8F325138                 loc_8F325138                                                ; CODE XREF: display_put_char+40
ROM:8F325138                                                                             ; display_put_char+5C
ROM:8F325138 010 50 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F32513A 010 1C 30                       ADDS    R0, #(cur_x - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F32513C 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F32513E 010 08 30                       ADDS    R0, #8                              ; Rd = Op1 + Op2
ROM:8F325140 010 4E 49                       LDR     R1, =0x8F32D870                     ; Load from Memory
ROM:8F325142 010 1C 31                       ADDS    R1, #(cur_x - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F325144 010 08 60                       STR     R0, [R1]                            ; Store to Memory
ROM:8F325146
ROM:8F325146                 nl_cr                                                       ; CODE XREF: display_put_char+10
ROM:8F325146                                                                             ; display_put_char+18 ...
ROM:8F325146 010 1D B1                       CBZ     R5, loc_8F325150                    ; Compare and Branch on Zero
ROM:8F325148 010 00 20                       MOVS    R0, #0                              ; Rd = Op2
ROM:8F32514A 010 4C 49                       LDR     R1, =0x8F32D870                     ; Load from Memory
ROM:8F32514C 010 1C 31                       ADDS    R1, #(cur_x - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F32514E 010 08 60                       STR     R0, [R1]                            ; Store to Memory
ROM:8F325150
ROM:8F325150                 loc_8F325150                                                ; CODE XREF: display_put_char:nl_cr
ROM:8F325150 010 36 B3                       CBZ     R6, return                          ; Compare and Branch on Zero
ROM:8F325152 010 4A 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F325154 010 18 30                       ADDS    R0, #(font_height - 0x8F32D870)     ; Rd = Op1 + Op2
ROM:8F325156 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F325158 010 48 49                       LDR     R1, =0x8F32D870                     ; Load from Memory
ROM:8F32515A 010 20 31                       ADDS    R1, #(cur_y - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F32515C 010 09 68                       LDR     R1, [R1]                            ; Load from Memory
ROM:8F32515E 010 01 44                       ADD     R1, R0                              ; Rd = Op1 + Op2
ROM:8F325160 010 46 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F325162 010 10 30                       ADDS    R0, #(lcd_height - 0x8F32D870)      ; Rd = Op1 + Op2
ROM:8F325164 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F325166 010 40 1C                       ADDS    R0, R0, #1                          ; Rd = Op1 + Op2
ROM:8F325168 010 81 42                       CMP     R1, R0                              ; Set cond. codes on Op1 - Op2
ROM:8F32516A 010 12 DC                       BGT     loc_8F325192                        ; Branch
ROM:8F32516C 010 43 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F32516E 010 18 30                       ADDS    R0, #(font_height - 0x8F32D870)     ; Rd = Op1 + Op2
ROM:8F325170 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F325172 010 42 49                       LDR     R1, =0x8F32D870                     ; Load from Memory
ROM:8F325174 010 20 31                       ADDS    R1, #(cur_y - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F325176 010 09 68                       LDR     R1, [R1]                            ; Load from Memory
ROM:8F325178 010 01 44                       ADD     R1, R0                              ; Rd = Op1 + Op2
ROM:8F32517A 010 13 31                       ADDS    R1, #0x13                           ; Rd = Op1 + Op2
ROM:8F32517C 010 3F 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F32517E 010 10 30                       ADDS    R0, #(lcd_height - 0x8F32D870)      ; Rd = Op1 + Op2
ROM:8F325180 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F325182 010 40 1C                       ADDS    R0, R0, #1                          ; Rd = Op1 + Op2
ROM:8F325184 010 81 42                       CMP     R1, R0                              ; Set cond. codes on Op1 - Op2
ROM:8F325186 010 04 DD                       BLE     loc_8F325192                        ; Branch
ROM:8F325188 010 00 20                       MOVS    R0, #0                              ; Rd = Op2
ROM:8F32518A 010 3C 49                       LDR     R1, =0x8F32D870                     ; Load from Memory
ROM:8F32518C 010 20 31                       ADDS    R1, #(cur_y - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F32518E 010 08 60                       STR     R0, [R1]                            ; Store to Memory
ROM:8F325190 010 06 E0                       B       return                              ; Branch
ROM:8F325192                 ; ---------------------------------------------------------------------------
ROM:8F325192
ROM:8F325192                 loc_8F325192                                                ; CODE XREF: display_put_char+96
ROM:8F325192                                                                             ; display_put_char+B2
ROM:8F325192 010 3A 48                       LDR     R0, =0x8F32D870                     ; Load from Memory
ROM:8F325194 010 20 30                       ADDS    R0, #(cur_y - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F325196 010 00 68                       LDR     R0, [R0]                            ; Load from Memory
ROM:8F325198 010 0B 30                       ADDS    R0, #0xB                            ; Rd = Op1 + Op2
ROM:8F32519A 010 38 49                       LDR     R1, =0x8F32D870                     ; Load from Memory
ROM:8F32519C 010 20 31                       ADDS    R1, #(cur_y - 0x8F32D870)           ; Rd = Op1 + Op2
ROM:8F32519E 010 08 60                       STR     R0, [R1]                            ; Store to Memory
ROM:8F3251A0
ROM:8F3251A0                 return                                                      ; CODE XREF: display_put_char:loc_8F325150
ROM:8F3251A0                                                                             ; display_put_char+BC
ROM:8F3251A0 010 70 BD                       POP     {R4-R6,PC}                          ; Pop registers
ROM:8F3251A0                 ; End of function display_put_char
ROM:8F3251A0
ROM:8F3251A2
ROM:8F3251A2                 ; =============== S U B R O U T I N E =======================================
ROM:8F3251A2
ROM:8F3251A2
ROM:8F3251A2                 ; int __fastcall display_put_string(char *string)
ROM:8F3251A2                 display_put_string                                          ; CODE XREF: display_draw_text+1E
ROM:8F3251A2                                                                             ; sub_8F3251B8+6C ...
ROM:8F3251A2 000 30 B5                       PUSH    {R4,R5,LR}                          ; Push registers
ROM:8F3251A4 00C 04 46                       MOV     R4, R0                              ; Rd = Op2
ROM:8F3251A6 00C 02 E0                       B       is_end_of_string                    ; Branch
ROM:8F3251A8                 ; ---------------------------------------------------------------------------
ROM:8F3251A8
ROM:8F3251A8                 is_a_usual_char                                             ; CODE XREF: display_put_string+12
ROM:8F3251A8 00C 28 46                       MOV     R0, R5                              ; ch
ROM:8F3251AA 00C FF F7 93 FF                 BL      display_put_char                    ; Branch with Link
ROM:8F3251AE
ROM:8F3251AE                 is_end_of_string                                            ; CODE XREF: display_put_string+4
ROM:8F3251AE 00C 14 F8 01 5B                 LDRB.W  R5, [R4],#1                         ; Load from Memory
ROM:8F3251B2 00C 00 2D                       CMP     R5, #0                              ; Set cond. codes on Op1 - Op2
ROM:8F3251B4 00C F8 D1                       BNE     is_a_usual_char                     ; Branch
ROM:8F3251B6 00C 30 BD                       POP     {R4,R5,PC}                          ; Pop registers
ROM:8F3251B6                 ; End of function display_put_string