NXP TDA19989

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NXP TDA19989AET is a very low power and very small size High-Definition Multimedia Interface (HDMI) v. 1.4 transmitter. It is backward compatible DVI 1.0 and can be connected to any DVI 1.0 and HDMI sink.

This device is primarily intended for mobile applications like Digital Video Camera (DVC), Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and Ultra-Mobile Personal Computer (UM PC) where size and very low power are mandatory for battery autonomy. It allows mixing 3 × 8-bit RGB or YCbCr video stream with a pixel rate up to 150 MHz together with one S/PDIF or two I2S-bus audio streams with an audio sampling rate up to 192 kHz.

In order to be compatible with most applications, TDA19989AET integrates a full programmable input formatter and color space conversion block. The video input formats accepted are YCbCr 4 :4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 × 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of ITU656-like format, the input pixel clock can be made active on one (SDR mode) or both edges (DDR mode). TDA19989AET includes a HDCP 1.3 compliant cipher block. The HDCP keys are stored internally in a non-volatile OTP memory for maximum security. This device provides additional embedded feature like CEC (Consumer Electronic Control). CEC is a single bidirectional wire that transmits CEC commands (like Standby from remote control) over the home appliance network connected through this wire. This eliminates the need of any additional device to handle this feature thus improving BOM (Bill Of Materials) of the whole system and enabling the connected devices (CEC enabled) to be controlled by only one remote control.

TDA19989AET supports xvYCC HDMI 1.4 feature.

It can be switched to very low power Standby or Sleep modes to save power when HDMI is not used. TDA19989AET includes I2C-bus master interface for DDC-bus communication for EDID reading and HDCP purpose. This device can be controlled or configured via I2C-bus interface.


  • Compliance:
    • DVI 1.0
    • HDMI 1.4
    • EIA/CEA-861B
    • CEC (HDMI 1.4)
    • SimplayHD
    • HDCP 1.3
  • Video:
    • xvYCC HDMI 1.4 feature
  • Video formats with a pixel rate up to 150 MHz:
    • RGB 4 : 4 : 4
    • YCbCr 4 : 4 : 4
    • YCbCr 4 : 2 : 2 semi-planar
    • YCbCr 4 : 2 : 2 ITU656
  • Maximum resolution:
    • 1080p for TV
    • 1600 × 1200 at 60 Hz for PC (UXGA60)
    • 720p/1080i in ITU656
  • Programmable color space converter:
    • RGB to YCbCr
    • YCbCr to RGB
  • Programmable input formatter and upsampler/interpolator allows input of any of the 4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656-like formats
  • Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or VREF, HREF and FREF could be used for input data synchronization*
  • Pixel clock input can be made active on one or both edges (selectable by I2C-bus)
  • Repetition of video samples as required by HDMI specification
  • Audio:
    • 2 × I2S-bus 2 channels or one S/PDIF; audio data rate up to 192 kHz
    • Deals with multiple levels of HDCP receivers and repeaters
  • Internal SHA-1 calculation
  • System operation:
    • Master DDC-bus interface for EDID read
    • Controllable via I2C-bus
  • Downstream availability through the use of hot plug detect (HPD) and receiver detection (RxSense)**
  • Package: TFBGA64 Size 4.5 × 4.5 × 0.95 mm
  • Power management:
    • External voltage supplies 1.8 V
    • Low power
    • Flexible power modes
  • Miscellaneous:
    • POR (Power-On Reset)
    • Audio and video inputs LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant
    • 250 MHz to 1.5 GHz TMDS transmitter operation

Datasheet: File:Tda19989aet datasheet.pdf

Application notes: File:Tda19989aet appnotes.pdf