Texas Instruments TMS320C6454

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Texas Instruments TMS320C6454 (on the OMAP3430 PoP package)

Description

The TMS320C64x+TM DSP is the new generation of the TMS320C64xTM DSP architecture. It presents some new features that did not exist in the C64xTM DSP architecture as well as some existing features that have been enhanced. The C64x+TM megamodule is the name used to designate the CPU together with the hardware providing memory, bandwidth management, interrupt, memory protection, and power-down support. This chapter provides an overview of the main components and features of the C64x+ megamodule. The C64x+ megamodule includes the following components: C64x+ CPU, Level 1 program (L1P) memory controller, Level 1 data (L1D) memory controller, Level 2 (L2) memory controller, Internal DMA (IDMA), bandwidth management (BWM), interrupt controller (INTC), power-down controller (PDC), and an extended memory controller (EMC).

The TMS320C64x+\x99 DSPs (including the TMS320C6454 device) are the highest-performance fixed-point DSP generation in the TMS320C6000\x99 DSP platform. The C6454 device is based on the third-generation high-performance, advanced VelociTI\x99 very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+\x99 devices are upward code-compatible from previous devices that are part of the C6000\x99 DSP platform.

Datasheets: http://xvilka.org/files/d-sheet/tms320c6454.tar.bz2